This invention relates to integrated circuit fabrication, and specifically to a method of shallow trench isolation (STI) using a single masking step.
Conventional STI, using dummy structures and/or reverse masking, is known to those of ordinary skill in the art. Each technique requires multiple steps and multiple masks during the fabrication process. The multiple steps and masks increase the cost of integrated circuits fabricated using conventional STI. Because of potential mask misalignment, integrated circuit reliability may suffer.
It is desirable to provide a method of STI which does not require multiple masking steps, nor which requires dummy structures.
A method of shallow trench isolation includes preparing a substrate, including forming mesa structures thereon; forming a barrier cap on the mesa structures; forming an oxide multi-layer structure over the mesas and barrier caps, including: depositing a first oxide layer having a conventional polishing rate, depositing a second oxide layer having a low polishing rate; and depositing a third oxide layer having a conventional polishing rate; and polishing the structure to the level of the barrier cap.
An object of the invention is to provide a method of eliminating extra masking steps for fabrication of devices using STI.
Another object of the invention is to provide a method of STI which does not require dummy structures.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.